1. Field of the Invention
The present invention generally relates to a memory access apparatus for reading out from a data memory the data corresponding to an index character inputted through an input unit, and more particularly concerns a memory access apparatus capable of reading out the data from the data memory at an increased speed.
The memory access apparatus can be, for example advantageously applied to a kana (i.e. Japanese phonetic alphabet)/kanji (Chinese character) translation apparatus for translating a word represented by kana spelling into a kanji word in a Japanese character input/output apparatus.
2. Description of the Related Art
In general, the number of words collected in a dictionary for translation of Japanese phonetic characters (hereinafter referred to as kana) into Chinese characters (hereinafter referred to as kanji) in a Japanese character input/output apparatus is a range of 30,000 to 50,000 although it varies diversely in dependence on the sophistication level of the apparatus. When the kana/kanji translation dictionary containing such number of words is to be stored in a memory, the capacity of the latter will amount to 250K bytes to several M bytes. The CPU used commonly in the Japanese character input/output apparatus is of 16 bits and has a memory space of 1 M bytes to tens M bytes. Accordingly, the capacity of the above mentioned kana/kanji translation dictionary memory can not be ignored in implementing the memory for the CPU. Particularly, in the case of the Japanese character input/output apparatus incorporating a CPU whose address space is 1 M bytes, a major proportion of the address space is occupied by a program memory and a character generator (CG) for storing character patterns, resulting in that the address space available for the kana/kanji translation dictionary memory is much restricted. As a consequence, the capacity of the dictionary has to be reduced. In case the contents of the dictionary can not be compressed to such an extent that the dictionary can be accommodated within the address space available for the kana/kanji translation dictionary memory, the dictionary can not be contained in the address space of the CPU but it must be stored in an external storage equipment, which in turn gives rise to a problem that the kana/kanji translation processing can not be accomplished at a high speed as desired. In this conjunction, Japanese Unexamined Patent Application Publication No. 150070/1982 discloses an approach for compressing the capacity of the dictionary to solve one of the problems which the prior art Japanese character input/output apparatus suffer. However, no consideration is paid as to how to deal with such case where the dictionary can not be compressed down to the capacity of the address space of a CPU secured for the kana/kanji translation dictionary memory.
As an attempt to allow the CPU to make access to a memory of such capacity which can not be accommodated within the address space of the CPU, there has been known a technique generally referred to as a bank switching method. According to this method, the memory is divided into a plurality of areas, wherein the memory is so controlled that one of the areas can be accessed by the CPU. By adopting this bank switching method, it is certainly possible to implement the kana/kanji translation dictionary memory for the Japanese character input/output apparatus incorporating a CPU having an address space with little margin without being equiped with any external storage device even in case the capacity of the dictionary can not be compressed. However, this type of dictionary control apparatus still involves a problem in realizing a high-speed kana/kanji translation processing due to inherent features of the kana/kanji translation dictionary and the kana/kanji translation processing as mentioned below.
In general, with a view to attaining a high-speed kana/kanji translation processing, the kana/kanji translation dictionary is composed of an index and a dictionary including a plurality of dictionary fields. In the dictionary, the words arrays, each including "kana spelling", "Chinese character (kanji)" and "grammatical information" are arranged sequentially in an alphabetic order of Japanese kanas, i.e. "a", "i", "u", "e", "o" and so on, according to the leading kana of the kana spellings in the respective arrays. Each of the dictionary fields includes those word arrays whose kana spellings begin with the same kana. In the index, there are registered the locations, i.e. the relative addresses, of the first word arrays in the respective dictionary fields relative to the leading address of the dictionary memory. The capacities of individual dictionary fields differ from one another. Moreover, since the individual dictionary fields are allotted closely to one another in the dictionary in an effort to compress the capacity of the dictionary, the locations of the individual dictionary fields or areas lack uniformity or regularity. Such being the circumstances, when the kana/kanji translation dictionary is divided into areas each having a certain constant capacity, there occurs such a situation in which one dictionary field will cover a plurality of areas. In general, in the kana/kanji translation processing for a given "kana spelling", random access is made to the index with the aid of the leading kana of that "kana spelling", being then followed by the access to the dictionary fields on the basis of the registered location information of the leading kana of the "kana spelling" in the ascending order of powers (hereinafter referred to as the sequential access) to retrieve the "kanji (Chinese character)" and "grammatical information" corresponding to the "kana spelling". Consequently, a major portion of the CPU's access to the memory storing the dictionary data is necessarily occupied by the sequential access. It is now apparent that in case the bank switching method is adopted for making access to the kana/kanji translation dictionary memory, there frequently occur such a situation in which the dictionary field covers a plurality of banks, which means that the bank switching process is required in the course of the sequential access to that dictionary field, reducing thus the kana/kanji translation processing speed, to a serious problem.
In addition to the bank switching technique mentioned above, there is also known a segment method developed by INTEL Co. Ltd., of U.S.A. According to this method, the address of 16 bits generated internally of a CPU is extended to 20 bits for creating an external address for the CPU. More specifically, the address data of 16 bits generated internally of the CPU is stored in a register referred to as the segment register and multiplied with 16, the resulting product being then added with the 16-bit address data generated subsequently internally of the CPU to be utilized as the external address for the CPU. With this arrangement, an external address of 20 bits can be outputted by using a 16-bit data internally available by the CPU, whereby 1 M byte is effectively available for the address space. The CPU can make access to the memory address space of 64K bytes selectively without need for rewriting the segment register incorporated in the CPU, and the memory address space of 65K bytes can be used to specify any given region or area within the memory address of 1 M bytes by rewriting the segment register. It is however noted that the proposed segment method is directed to extend the address bus of the CPU and not intended for application to the kana/kanji translation dictionary memory for accomplishing the high-speed kana/kanji translation processing.